1. Technical Field
The present application relates generally to a digital phase shifter and, more particularly, to an apparatus and method for providing an improved hardware implementation of a digital phase shifter.
2. Description of the Related Art
Modern communications systems often require the implementation of complex digital signal processing algorithms. One such algorithm is used in a conventional digital phase shifter (or mixer). A digital phase shifter is a key functional component in a large number of modern communication systems such as Direct Satellite System (DSS) receivers, digital cellular phones, satellite modems, and wireless local area network (LAN) modems. In particular, one important application of the digital phase shifter is in a digital phase-locked loop (PLL) which is used to remove phase and/or frequency error from a received signal. The use of digital PLLs simplify system design by obviating the need for external analog voltage-controlled oscillators and associated circuitry.
Referring now to FIG. 1, a block diagram illustrates a conventional digital communications demodulator having a digital phase shifter. The operation of the conventional digital phase shifter will be described in the context of the digital communications demodulator since this is one of its primary applications. In the system diagram of FIG. 1, a radio signal is received by an antenna 10 and then translated from a carrier frequency to baseband (or xe2x80x9czero-IFxe2x80x9d) I and Q signals by a quadrature demodulator 12. The baseband I and Q signals (i.e., complex signals) respectively refer to the xe2x80x9cin-phasexe2x80x9d and xe2x80x9cquadrature phasexe2x80x9d components of the radio signal. As shown in FIG. 2, the I and Q baseband signals form a complex vector xe2x80x9czxe2x80x9d in a cartesian plane, where the tip of the vector xe2x80x9czxe2x80x9d is equal to (I+jQ). In addition z, I and Q can be represented as a function of time using the functional notation z(t)=I(t)+jQ(t), where xe2x80x9cjxe2x80x9d is equal to the square root of negative 1, and represents a location in the Cartesian plane of (0,1).
Referring back to FIG. 1, the analog I and Q signals from the quadrature demodulator 12 are digitized by a first analog-to-digital (A/D) converter 14 and a second A/D converter 16, respectively, and the digitized I and Q signals are sent to a digital demodulator 18. The digital demodulator 18 includes a digital phase shifter (mixer) 20 which receives the digitized I and Q signals and mixes them with a locally generated phase reference xcfx86(n) so as to apply a phase correction to the digitized samples. The phase is normally updated on a sample-by-sample basis so that the system can remove the phase error effects due to frequency offset or other dynamic phase fluctuations which may occur during transmission in the radio channel. The phase-corrected samples are then integrated by a matched-filter correlator 22 which produces an estimate of the transmitted information symbol. The transmitted information symbol is transformed into information bits (data) by a decoder 24.
The phase reference xcfx86(n) is typically provided by a carrier recovery module 26 which utilizes an algorithm that is driven by symbol decision-error directed computations provided by the decoder 24. The carrier recovery module 26 determines the correct phase xcfx86(n) to apply to the digital phase shifter 20 in order to cancel the phase error on the digitized I/Q samples that are received by the digital demodulator 18. In particular, the digital phase shifter 20 rotates the vector z=I+jQ (which represents corresponding I/Q samples) by the phase reference angle xcfx86(n). Mathematically, the rotation of the complex vector. xe2x80x9czxe2x80x9d by phase xe2x80x9cxcfx86xe2x80x9d is accomplished through multiplication with a complex exponential ejxcfx86 (i.e., (I+jQ)*ejxcfx86).
Typically, conventional digital phase shifters used in high data rate systems such as DSS receivers or high speed wireless LANs are implemented in hardware. The conventional hardware-based digital phase shifter employs a read-only memory. (ROM) lookup table and a complex-multiply operation. Referring now to FIG. 3, a block diagram illustrates a conventional hardware realization for a conventional digital phase shifter, such as the one shown in FIG. 1. In FIG. 3, I(n) and Q(n) represent discrete samples which are received by the digital phase shifter 20, xcfx86(n) represents the correction phase applied to the input I(n) and Q(n) samples, and Iout(n) and Qout(n) represent the phase-corrected samples output from the digital phase shifter 20. The digital phase shifter 20 includes a complex multiply module 20b which multiplies the input samples I(n) and Q(n) (i.e., I(n)+jQ(n)) by the complex exponential ejxcfx86. Specifically, since ejxcfx86=cos(xcfx86)+jsin(xcfx86) by Euler""s identity, the complex multiply module 20b performs a fast phase-rotation by first retrieving the values for cos(xcfx86) and sin(xcfx86) from a lookup ROM 20a, and then performing one complex multiplication (i.e., [I(n)+jQ(n)]*[cos(xcfx86)+jsin(xcfx86)]) to form the phase-rotated output samples (i.e., Iout(n)=I(n) cos(xcfx86)xe2x88x92Q(n) sin(xcfx86) and Qout(n)=I(n) sin(xcfx86)+Q(n) cos(xcfx86)).
As shown, the complex multiplication requires four multiplications and two additions to generate the phase-corrected output samples. The complex multiplication process of the conventional digital phase shifter 20 requires the implementation of sophisticated digital multipliers. There is a need, therefore, for an improved hardware-based digital phase shifter which utilizess a simplified phase correction process and obviates the need for the complex digital multipliers and ROM of the conventional hardware-based digital phase shifter.
The present application is directed to an apparatus and method for an improved hardware implementation of a digital phase shifter which provides a simplified process for phase correction of digital signals and eliminates the use of a lookup ROM and complex digital multipliers. The present digital phase shifter operates by applying a phase correction to digital samples in separate phase-shift stages, where each phase-shift stage performs a phase rotation by an amount specified directly by the binary values of an integer input phase.
In one aspect, an apparatus for applying a phase shift to a complex digital signal, comprises: a plurality of phase shift stages each having a phase shift value associated therewith, whereby each of said plurality of phase shift stages selectively applies the corresponding phase shift value to the complex digital signal.